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Dual MOSFET Driver with Bootstrapping ADP3415
FEATURES All-in-One Synchronous Buck Driver One PWM Signal Generates Both Drives Anticross Conduction Protection Circuitry Programmable Transition Delay Zero-Crossing Synchronous Drive Control Synchronous Override Control Undervoltage Lockout Shutdown Quiescent Current <100 A APPLICATIONS Mobile Computing CPU Core Power Converters Multiphase Desktop CPU Supplies Single-Supply Synchronous Buck Converters Standard-to-Synchronous Converter Adaptations FUNCTIONAL BLOCK DIAGRAM
ADP3415
VCC UVLO BST IN SD DLY OVERLAP PROTECTION CIRCUIT DRVH SW
VCC DRVL
DRVLSD GND
GENERAL DESCRIPTION
The ADP3415 is a dual MOSFET driver optimized for driving two N-channel FETs that are the two switches in the nonisolated synchronous buck power converter topology. Each driver size is optimized for performance in notebook PC regulators for CPUs in the 20 A range. The high-side driver can be bootstrapped atop the switched node of the buck converter as needed to drive the upper switch and is designed to accommodate the high voltage slew rate associated with high performance, high frequency switching. The ADP3415 features an overlapping protection circuit (OPC); undervoltage lockout (UVLO) that holds the switches off until the driver is assured of having sufficient voltage for proper operation; a programmable transition delay; and a synchronous drive disable pin. The quiescent current, when the device is disabled, is less than 100 A. The ADP3415 is specified over the extended commercial temperature range of 0C to 100C and is available in a 10-lead MSOP package.
5V
VDCIN
FROM DUTY RATIO MODULATOR FROM SYSTEM ENABLE CONTROL FROM SYSTEM STATE LOGIC
IN SD
VCC
BST DRVH
ADP3415
DRVLSD SW
VOUT
DLY GND
DRVL
Figure 1. Typical Application Circuit
(c)2010 SCILLC. All rights reserved. May 2010 - Rev. 6
Publication Order Number: ADP3415/D
ADP3415-SPECIFICATIONS1
Parameter SUPPLY (VCC) Quiescent Current2 Shutdown Mode Operating Mode UNDERVOLTAGE LOCKOUT (UVLO) UVLO Threshold UVLO Hysteresis LOW-SIDE DRIVER SHUTDOWN (DRVLSD) Input Voltage High3 Input Voltage Low3 Propagation Delay3, 4 (See Figure 3) SHUTDOWN (SD) Input Voltage High3 Input Voltage Low3 INPUT (IN) Input Voltage High3 Input Voltage Low3 THERMAL SHUTDOWN (THSD) THSD Threshold THSD Hysteresis HIGH-SIDE DRIVER (DRVH) Output Resistance, DRVH-BST Output Resistance, DRVH-SW DRVH Transition Times4 (See Figure 4) DRVH Propagation Delay4, 5 (See Figure 4) LOW-SIDE DRIVER (DRVL) Output Resistance, DRVL-VCC Output Resistance, DRVL-GND DRVL Transition Times4 (See Figure 4) DRVL Propagation Delay4, 5, 6 (See Figure 4) SW Transition Timeout7 Zero-Crossing Threshold Symbol ICCQ
(TA = 0 C to 100 C, VCC = 5 V, VBST - VSW = 5 V, SD = 5 V, CDRVH = CDRVL = 3 nF, unless otherwise noted.)
Conditions Min Typ Max Unit
VSD = 0.8 V VSD = 5 V, No Switching
30 1.2
65 2
A mA
VCCUVLO VCCHUVLO
3.9
4.15 0.05
4.5
V V
VIH VIL tpdlDRVLSD tpdhDRVLSD VIH VIL VIH VIL TSD THSD TJ = TA TJ = TA
2.0 20 10 2.0 0.8 2.0 0.8 165 10 1.5 0.85 20 25 22 40 1.6 1.0 25 20 30 10 1.6 3.5 2.0 30 35 40 200 70 3.0 3.0 40 30 38 25 300 0.8 50 30
V V ns ns V V V V C C ns ns ns ns ns ns ns ns ns ns V
trDRVH tfDRVH tpdhDRVH tpdlDRVH
VBST - VSW = 4.6 V VBST - VSW = 4.6 V, VDLY = 0 V RDLY 120 k 10 100
trDRVL tfDRVL tpdhDRVL tpdlDRVL tSWTO VZC
VBST - VSW = 4.6 V VBST - VSW = 4.6 V VBST - VSW = 4.6 V VBST - VSW = 4.6 V VBST - VSW = 4.6 V
10 130
NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 Including IBSTQ quiescent current. 3 The signal source driving the pin must have 70 A (typ) pull-down strength to make a high-to-low transient, and 20 A (typ) pull-up strength to make a low-to-high transient. The pin does not represent load (<100 nA) in static low (<0.8 V) and static high (>2.0 V) logic states (see TPC 3.) The pin can be driven with standard TTL logic level source. 4 Guaranteed by characterization. 5 For propagation delays, tpdh refers to the specified signal going high, tpdl refers to it going low. 6 Propagation delay measured until DRVL begins its transition. 7 The turn-on of DRVL is initiated after IN goes low by either V SW crossing a ~1.6 V threshold or by expiration of t SWTO. Specifications subject to change without notice.
Rev. 6 | Page 2 of 10 | www.onsemi.com
-2-
REV. B
ADP3415
ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V BST to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +30 V BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V SW to GND . . . . . . . . . . . . . . . . . . . . . . . . . -2.0 V to +25 V SD, IN, DRVLSD to GND . . . . . . . . . . . . . . -0.3 V to +7.3 V Operating Ambient Temperature Range . . . . . . 0C to 100C Operating Junction Temperature Range . . . . . . 0C to 125C JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155C/W JC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C/W Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND.
IN 1 SD 2
10 BST
9 DRVH TOP VIEW DRVLSD 3 (Not to Scale) 8 SW
ADP3415
DLY 4 VCC 5
7 6
GND DRVL
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2 3 4 5 6 7 8
Mnemonic IN SD DRVLSD DLY VCC DRVL GND SW
Function TTL-Level Input Signal. Has primary control of the drive outputs. Shutdown. When high, this pin enables normal operation. When low, DRVH and DRVL are forced low and the supply current (ICCQ) is minimized as specified. Drive-Low Shutdown. When DRVLSD is low, DRVL is kept low. When DRVLSD is high, DRVL is enabled and controlled by IN and by the adaptive OPC function. High-Side Turn-On Delay. A resistor from this pin to ground programs an extended delay from turn-off of the lower FET to turn-on of the upper FET. Input Supply. This pin should be bypassed to GND with a ~10 F ceramic capacitor. Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) FET. Ground. Should be directly connected to the ground plane, close to the source of the lower FET. This pin should be connected to the buck switching node, close to the upper FET's source. It is the floating return for the upper FET drive signal. Also, it is used to monitor the switched voltage for the OPC function. Buck Drive. Output drive for the upper (buck) FET. Floating Bootstrap Supply for the Upper FET. A capacitor connected between BST and SW pins holds this bootstrapped supply voltage for the high-side FET driver as it is switched. The capacitor should be an MLC type and should have substantially greater capacitance (e.g., ~ 20x) than the input capacitance of the upper FET.
9 10
DRVH BST
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3415 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 6 | Page 3 of 10 | www.onsemi.com
ADP3415
VCC VCC UVLO VUVLOTH SD BIAS THERM SD THSD BST IN DRVH TON DLY DLY RDLY VCC R DRVL TON DLY DRVLSD Q S GND DRVL Q2 SET R CLR Q S + DRVH CBST Q1 VTOK BIAS EN DBST VDCIN
SW
ADP3415
Figure 2. Functional Block Diagram
IN
DRVLSD
tpdlDRVLSD
DRVL
tpdhDRVLSD
Figure 3. DRVLSD Propagation Delay
Rev. 6 | Page 4 of 10 | www.onsemi.com
-4-
REV. B
ADP3415
IN
tpdl DRVL
DRVL
tpdl DRVH tf DRVL tpdh DRVH tr DRVL
tpdh DRVL
DRVH-SW
tr DRVH
tf DRVH
Figure 4. Switching Timing Diagram (Propagation Delay Referenced to 50%, Rise and Fall Time to 10% and 90% Points)
IN
tSWTO
DRVL CROWBAR ACTION
SW
DRVH
Figure 5. Switching Waveforms-SW Node Failure Mode-DRVL Timeout
Rev. 6 | Page 5 of 10 | www.onsemi.com
ADP3415-Typical Performance Characteristics
37
2V/DIV
35
VCC = 5V CLOAD = 3nF
DRVH
33 RISE TIME 31
DRVL
TIME - ns
29 27
IN
25 FALL TIME
20ns/DIV TIME - ns
VCC = 5V CLOAD = 3nF VSW = 0V
23 21 0 25 50 75 100 125 JUNCTION TEMPERATURE - C
TPC 1. DRVH Fall and DRVL Rise Times
TPC 4. DRVL Rise and Fall Times vs. Temperature
30
2V/DIV
VCC = 5V CLOAD = 3nF 28 FALL TIME 26
DRVL
TIME - ns
DRVH
24
22 RISE TIME
IN
20
VCC = 5V CLOAD = 3nF RDLY = 40k TIME - ns
18
20ns/DIV
16 0 25 50 75 100 125 JUNCTION TEMPERATURE - C
TPC 2. DRVL Fall and DRVH Rise Times
TPC 5. DRVH Rise and Fall Times vs. Temperature
100 90 80 VCC = 5V TA = 25 C CLOAD = 3nF
70 VCC = 5V TA = 25 C 60
PEAK CURRENT - A
70 50
50 40 30 20
TIME - ns
60
HIGH-TO-LOW TRANSITION
DRVL 40
30
DRVH
20 10 0 0 1 2 3 INPUT VOLTAGE - V 4 5 LOW-TO-HIGH TRANSITION 10 1 2 3 4 5 6 7 8 9 10 LOAD CAPACITANCE - nF
TPC 3. Input Voltage vs. Input Current
TPC 6. DRVH and DRVL Rise Time vs. Load Capacitance
Rev. 6 | Page 6 of 10 | www.onsemi.com
-6-
REV. B
ADP3415
VCC = 5V 47 CLOAD = 3nF 42 37 52 45 40 VCC = 5V TA = 25 C CLOAD = 3nF
tpdlDRVH
SUPPLY CURRENT - mA
125
35 30 25 20 15 10 5 0 200
TIME - ns
32 27 22 17 12 7 2 0 25 50 75 100 JUNCTION TEMPERATURE - C
tpdlDRVL
400
600 800 IN FREQUENCY - kHz
1000
1200
TPC 7. DRVH and DRVL Propagation Delay vs. Temperature
10.5 52 47 42 37 TIME - ns 32 27 22 17 12 7 1 2 3 4 7 5 6 LOAD CAPACITANCE - nF 8 9 10 DRVH DRVL VCC = 5V TA = 25 C 10.0 9.5
TPC 10. Supply Current vs. Frequency
SUPPLY CURRENT - mA
9.0 8.5 8.0 7.5 7.0 6.5 6.0 VCC = 5V fIN = 250kHz CLOAD = 3nF 0 25 50 75 100 JUNCTION TEMPERATURE - C 125
TPC 8. DRVH and DRVL Fall Time vs. Load Capacitance
TPC 11. Supply Current vs. Temperature
182 162 142 122
VCC = 5V fIN = 200kHz CLOAD = 3nF OPEN DELAY PIN
TIME - ns
102 82 62 42 SHORTED TO GROUND 22 2
0
25
50 75 100 JUNCTION TEMPERATURE - C
125
TPC 9. tpdhDRVH vs. Temperature
Rev. 6 | Page 7 of 10 | www.onsemi.com
REV. B
-7-
ADP3415
THEORY OF OPERATION
The ADP3415 is a dual MOSFET driver optimized for driving two N-channel FETs in a synchronous buck converter topology. A single duty ratio modulation signal is all that is required to command the proper drive signal for the high-side and the low-side FETs. A more detailed description of the ADP3415 and its features follows. Refer to the Functional Block Diagram (Figure 2).
Drive State Input
The drive state input, IN, should be connected to the duty ratio modulation signal of a switch-mode controller. IN can be driven by 2.5 V to 5.0 V logic. The FETs will be driven so that the SW node follows the polarity of IN.
Low-Side Driver
overlap protection circuit waits for the voltage at the SW pin to fall from VDCIN to 1.6 V. Once the voltage on the SW pin has fallen to 1.6 V, Q2 will begin to turn ON. By waiting for the voltage on the SW pin to reach 1.6 V, the overlap protection circuit ensures that Q1 is OFF before Q2 turns on, regardless of variations in temperature, supply voltage, gate charge, and drive current. There is, however, a timeout circuit that will override the waiting period for the SW pin to reach 1.6 V. After the timeout period has expired, DRVL will be asserted regardless of the SW voltage. To prevent the overlap of the gate drives during Q2's turn OFF and Q1's turn ON, the overlap circuit provides a programmable delay that is set by a resistor on the DLY pin. When IN goes high, Q2 will begin to turn OFF (after a propagation delay), but before Q1 can turn ON, the overlap protection circuit waits for the voltage at DRVL to go low. Once the voltage at DRVL is low, the overlap protection circuit initiates a delay timer that is programmed by the external resistor RDLY. The delay resistor adds an additional specified delay. The delay allows time for current to commutate from the body diode of Q2 to an external Schottky diode, which allows turn-off losses to be reduced. Although not as foolproof as the adaptive delay, the programmable delay adds a safety margin to account for variations in size, gate charge, and internal delay of the external power MOSFETs.
Low-Side Driver Shutdown
The supply rails for the low-side driver, DRVL, are VCC and GND. In its conventional application, it drives the gate of the synchronous rectifier FET. When the driver is enabled, the driver's output is 180 out of phase with the duty ratio input aside from overlap protection circuit, propagation, and transition delays. When the driver is shut down or the entire ADP3415 is in shutdown or in undervoltage lockout, the low-side gate is held low.
High-Side Driver
The supply rail for the high-side driver, DRVH, is between the BST and SW pins and is created by an external bootstrap supply circuit. In its conventional application, it drives the gate of the (top) main buck converter FET. The bootstrap circuit comprises a Schottky diode, DBST, and bootstrap capacitor, CBST. When the ADP3415 is starting up, the SW pin is at ground, so the bootstrap capacitor will charge up to VCC through DBST. As the supply voltage ramps up and exceeds the UVLO threshold, the driver is enabled. When the input pin, IN, goes high, the high-side driver will begin to turn the high-side FET (Q1) ON by transferring charge from CBST to the gate of the FET. As Q1 turns ON, the SW pin will rise up to VDCIN, forcing the BST pin to VDCIN + VC(BST), which is enough gate to source voltage to hold Q1 ON. To complete the cycle, when IN goes low, Q1 is switched OFF as DRVH discharges the gate to the voltage at the SW pin. When the low-side FET, Q2, turns ON, the SW pin is held at ground. This allows the bootstrap capacitor to charge up to VCC again. The high-side driver's output is in phase with the duty ratio input. When the driver is in undervoltage lockout, the high-side gate is held low.
Overlap Protection Circuit
The low-side driver shutdown, DRVLSD, allows a control signal to shut down the synchronous rectifier. This signal should be modulated by system state logic to achieve maximum battery life under light load conditions and maximum efficiency under heavy load conditions. Under heavy load conditions, DRVLSD should be high so that the synchronous switch is modulated for maximum efficiency. Under light load conditions, DRVLSD should be low to prevent needless switching losses due to charge shuttling caused by polarity reversal of the inductor current when the average current is low. When the DRVLSD input is low, the low-side driver stays low. When the DRVLSD input is high, the low-side driver is enabled and controlled by the driver signals as previously described.
Low-Side Driver Timeout Circuit
The overlap protection circuit (OPC) prevents both of the main power switches, Q1 and Q2, from being ON at the same time. This prevents excessive shoot-through currents from flowing through both power switches and minimizes the associated losses that can occur during their ON-OFF transitions. The overlap protection circuit accomplishes this by adaptively controlling the delay from Q1's turn OFF to Q2's turn ON and by programming the delay from Q2's turn OFF to Q1's turn ON. To prevent the overlap of the gate drives during Q1's turn OFF and Q2's turn ON, the overlap circuit monitors the voltage at the SW pin. When IN goes low, Q1 will begin to turn OFF (after a propagation delay), but before Q2 can turn ON, the
In normal operation, the DRVH signal tracks the IN signal and turns OFF the Q1 high-side switch with a few tens of ns tpdlDRVH delay following the falling edge of the input signal. When Q1 is turned OFF, then DRVL is allowed to go high, Q2 to turn ON, and the SW node voltage to collapse to zero. But in a faulty scenario, such as the case of a high-side Q1 switch drain-source short circuit when even DRVH goes low, the SW node cannot fall to zero. The ADP3415 has a timer circuit to address this scenario. Every time the IN goes low, a DRVL on-time delay timer gets triggered (see Figure 2). Should the SW node voltage not trigger the low side turn-on, the DRVL on-time delay circuit will do it instead, when it times out with tSWTO delay (see Figure 5). If the high-side Q1 is still turned ON, i.e., its drain is shorted to the source, the low-side Q2 turn-on will create a direct short circuit across the VDCIN voltage rail, and the crowbar action will blow the fuse in the VDCIN current patch. The opening of the fuse saves the load (CPU) from potential damage that the high-side switch short circuit could have caused.
Rev. 6 | Page 8 of 10 | www.onsemi.com
-8-
REV. B
ADP3415
Shutdown Bootstrap Circuit
For optimal system power management, when the output voltage is not needed, the ADP3415 can be shut down to conserve power. When the SD pin is high, the ADP3415 is enabled for normal operation. Pulling the SD pin low forces the DRVH and DRVL outputs low, turning the buck converter OFF and reducing the VCC supply current to less than 40 A.
Undervoltage Lockout
The bootstrap circuit requires a charge storage capacitor, CBST, and a Schottky diode, D1, as shown in Figure 2. Selecting these components can be done after the high-side FET has been chosen. The bootstrap capacitor must have a voltage rating that is able to handle the maximum battery voltage plus 5 V. The capacitance is determined using the following equation CBST = QGATE VBST (1)
The undervoltage lockout (UVLO) circuit holds both FET driver outputs low during VCC supply ramp-up. The UVLO logic becomes active and in control of the driver outputs at a supply voltage of no greater than 1.5 V. The UVLO circuit waits until the VCC supply has reached a voltage high enough to bias logic level FETs fully ON, around 4.1 V, before releasing control of the drivers to the control pins.
Thermal Shutdown
where QGATE is the total gate charge of the high-side FET, and VBST is the voltage droop allowed on the high-side FET drive. For example, the IRFR8503 has a total gate charge of about 15 nC. For an allowed droop of 150 mV, the required bootstrap capacitance is 100 nF. Use an MLC capacitor. A Schottky diode is recommended for the bootstrap diode due to its low forward drop, which maximizes the drive available for the high-side FET. The bootstrap diode must also be able to withstand the maximum battery voltage plus 5 V. The average forward current can be estimated by
IF ( AVG ) QGATE x f MAX
The thermal shutdown circuit protects the ADP3415 against damage due to excessive power dissipation. Under extreme conditions, high ambient temperature and high power dissipation, the die temperature may rise up to the thermal shutdown threshold of 165C. If the die temperature exceeds 165C, the thermal shutdown circuit will turn the output drivers OFF. The drivers remain disabled until the junction temperature has decreased by 10C, at which point the drivers are again enabled.
APPLICATION INFORMATION Supply Capacitor Selection
(2)
where fMAX is the maximum switching frequency of the controller.
Delay Resistor Selection
For the supply input (VCC) of the ADP3415, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn. Use a 10 F MLC capacitor. Keep the ceramic capacitor as close as possible to the ADP3415. Multilayer ceramic (MLC) capacitors provide the best combination of low ESR and small size and can be obtained from the following vendors: Murata Taiyo-Yuden Tokin GRM235Y5V106Z16 EMK325F106ZF C23Y5V1C106ZP www.murata.com www.t-yuden.com www.tokin.com
The delay resistor, RDLY, is used to add an additional delay when the low-side FET drive turns off and when the high-side drive starts to turn on. The delay resistor programs a specified additional delay besides the 20 ns of fixed delay.
Printed Circuit Board Layout Considerations
Use the following general guidelines when designing printed circuit boards: 1. Trace out the high current paths and use short, wide traces to make these connections. 2. Locate the VCC bypass capacitor as close as possible to the VCC and GND pins.
Rev. 6 | Page 9 of 10 | www.onsemi.com
REV. B
-9-
ADP3415
OUTLINE DIMENSIONS 10-Lead Micro Small Outline Package [MSOP] (RM-10)
Dimensions shown in millimeters
3.00 BSC
10
6
3.00 BSC
1 5
4.90 BSC
PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.00 0.27 0.17
1.10 MAX 8 0 0.80 0.60 0.40
SEATING PLANE
0.23 0.08
COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA
Model ADP3415LRM-REEL ADP3415LRM-REEL7 ADP3415LRMZ-REEL ADP3415LRMZ-RL7
1
Temperature Range 0C to 100C 0C to 100C
1
Package Description MSOP MSOP MSOP MSOP
Package Option RM-10 RM-10 RM-10 RM-10
Quanity Per Reel 3,000 1,000 3,000 1,000
Branding P1E P1E P1E P1E
0C to 100C 0C to 100C
1
Z = Pb-Free part
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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